Training
TideLM does real gradient-based fine-tuning. Metadata edits, prompt wrappers, and renamed checkpoints do not count.
Reference pass
python3 -m venv .venv
. .venv/bin/activate
pip install -e '.[train]'
tidelm data prepare
tidelm data tokenize --max-length 160
tidelm train --config configs/train-cpu-v0.1.0.json
The reference CPU configuration is deliberately small and explicit:
| Setting | Value |
|---|---|
| Parent | pinned SmolLM3-3B BF16 |
| Dataset | TideSet 0.1.0 |
| Train / validation | 22 / 5 records |
| Target | final layer (35) q_proj, v_proj |
| LoRA rank / alpha | 8 / 16 |
| Trainable parameters | measured at runtime |
| Sequence limit | 160 tokens; silent truncation forbidden |
| Optimizer | AdamW |
| Learning rate | 5e-4 |
| Planned optimizer steps | 12 |
| Prompt loss | masked; assistant targets only |
| Seed | 240826 |
“Planned” values become results only after the run completes. Actual duration, hardware, peak RSS, every step loss, validation loss, outputs, artifact hashes, and errors are stored under the immutable experiment ID.
Memory strategy
The constrained reference host has no GPU. It loads native BF16 and trains LoRA only in the final transformer block, so frozen earlier layers do not retain an autograd graph. This is not equivalent to full-model training and will be reported as a narrow adaptation. No unsupported CPU quantization is silently substituted.
Failure behavior
The runner creates a new output directory and refuses to overwrite it. An exception writes status: failed, traceback, duration, and peak memory to the run record and registry. Retry with a new experiment ID; never erase the failed pass.
Reproduction limits
CPU BF16 kernels and thread scheduling can alter timing and low-order floating point behavior. Seeds and data order are fixed, but exact bitwise equality across hardware is not promised. Adapter hashes are the identity of a published run.